Design of Low Power Explicit Pulse Triggered Flip Flop
نویسندگان
چکیده
D flip flop is one of the fundamental building blocks in most digital designs. Many high speed digital circuits such as memory require high speed and low power consumption. In existing method, the charge keeper is used to provide strong 0 and strong 1 since it uses pass transistor for signal feed through technique. A new D Flip Flop is proposed with signal feed through technique using transmission gate, where the circuit of the existing method is modified for low power dissipation and to reduce the number of transistor count. The proposed method is implemented using Mentor Graphics 11.6 at 130nm Technology.
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